Patterning Sub-30-nm MOSFET Gate with -Line Lithography
نویسندگان
چکیده
We have investigated two process techniques: resist ashing and oxide hard mask trimming. A combination of ashing and trimming produces sub-30-nm MOSFET gate. These techniques require neither specific equipment nor materials. These can be used to fabricate experimental devices with line width beyond the limit of optical lithography or high-throughput -beam lithography. They provide 25-nm gate pattern with -line lithography and sub-20-nm pattern with -beam lithography. A 40-nm gate channel length nMOSFET is demonstrated.
منابع مشابه
Electron beam lithography patterning of sub-10 nm line using hydrogen silsesquioxane for nanoscale device applications
We investigated novel patterning techniques to produce ultrafine patterns for nanoscale devices. Hydrogen silsesquioxane HSQ was employed as a high-resolution negative tone inorganic electron beam resist. The nanoscale patterns with sub-10 nm linewidth were successfully formed. A trimming process of HSQ by the reactive ion etcher RIE played an important role for the formation of 5 nm nanowire p...
متن کاملMultiple Nanowire Gate Field Effect Transistors
Novel metal oxide semiconductor field effect transistor (MOSFET) architectures aimed at sub IV operation with enhanced current driving capability are reported. In our design, the planar channel region in a conventional MOSFET is replaced by an array of isolated Si wires. Directional metal coverage of the two sidewalls and the top surface of each Si wire help achieve enhanced gate control. Sub I...
متن کاملTechnology of FinFET for High RF and Analog/Mixed-Signal Performance Circuits
In this paper, we discuss the process, layout and device technologies of FinFET to obtain high RF and analog/mixed-signal performance circuits. The fin patterning due to Side-wall transfer (SWT) technique is useful to not only fabricate narrow fin line but also suppress the fin width variation comparing with ArF and EB lithography. The H2 annealing after Si etching is useful for not only to imp...
متن کاملA 3-D Atomistic Study of Archetypal Double Gate MOSFET Structures
The double gate MOSFET architecture has been proposed as a possible solution to allow the scaling of MOSFETs to the sub-30 nm regime, particularly due to its inherent resistance to short-channel effects. The use of lightly doped, or even undoped, channels means that such devices should be inherently resistant to random dopant induced fluctuations which will be one of the major obstacles to MOSF...
متن کاملFull 3D Statistical Simulation of Line Edge Roughness in sub-100nm MOSFETs
Line Edge Roughness (LER), caused by tolerances inherent to materials and tools used in lithography processes, is not a new phenomenon. Yet, the imperfections caused by LER have caused little worry over the years since the critical dimensions of MOSFETs were almost two orders of magnitude larger than the roughness. However, as the aggressive scaling of Si-MOSFETs continues to the sub-100 nm reg...
متن کامل